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Checkpoint: paired ACL-TTL overhead measurement, 9/18 cells (halfway)

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Cells 7-9 complete and verified (480/480 rows, 16/16 cfg coverage, zero
errors each): aarch64/13579 enabled, amd64/13579 disabled,
amd64/12345 disabled.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
2026-08-20 18:48:25 -04:00
co-authored by Claude Sonnet 5
parent e7b7f45d60
commit 1880e78a1a
8 changed files with 49718 additions and 0 deletions
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experiments/bare_metal/runs/acl-ttl-overhead-20260820/timing.csv
+3
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@@ -5,3 +5,6 @@ order,arch,seed,acl,start_ts,end_ts,elapsed_s,rows,cfgs_ok,errors
4,aarch64,12345,enabled,1787263540.138566609,1787263850.633268709,310.495,480,TRUE,0
5,riscv64,13579,disabled,1787263959.600081018,1787264116.655408410,157.055,480,TRUE,0
6,aarch64,12345,disabled,1787264494.120355867,1787264777.160787083,283.040,480,TRUE,0
7,aarch64,13579,enabled,1787264974.177469213,1787265291.239105652,317.062,480,TRUE,0
8,amd64,13579,disabled,1787265488.338670740,1787265680.056553038,191.718,480,TRUE,0
9,amd64,12345,disabled,1787265875.831736966,1787266064.967044192,189.135,480,TRUE,0
1 order arch seed acl start_ts end_ts elapsed_s rows cfgs_ok errors
5 4 aarch64 12345 enabled 1787263540.138566609 1787263850.633268709 310.495 480 TRUE 0
6 5 riscv64 13579 disabled 1787263959.600081018 1787264116.655408410 157.055 480 TRUE 0
7 6 aarch64 12345 disabled 1787264494.120355867 1787264777.160787083 283.040 480 TRUE 0
8 7 aarch64 13579 enabled 1787264974.177469213 1787265291.239105652 317.062 480 TRUE 0
9 8 amd64 13579 disabled 1787265488.338670740 1787265680.056553038 191.718 480 TRUE 0
10 9 amd64 12345 disabled 1787265875.831736966 1787266064.967044192 189.135 480 TRUE 0