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aarch64: GIC SPI wiring for virtio-input (item 4.3.5d)

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Punch list §25 item 4.3.5d complete.

New apic_spi_enable(intid) generalizes item 0.6's PPI-only sequence to one
explicit SPI (IPRIORITYR/ISENABLER/ITARGETSR, ICFGR read-checked not
written). Verified via a software-pended SPI (GICD_ISPENDR, no device
needed) through the existing generic IRQ dispatch, which needed no changes.
Found and fixed a real bug during verification: PSTATE.I is still set at
apic_init()'s point in boot, so the first self-test run correctly latched
but never took the interrupt. Self-test code reverted after capturing
evidence -- interrupts.c has zero net diff, only apic_spi_enable() remains,
unused until 4.3.5e. Three-arch acceptance boot clean.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
2026-08-08 12:15:23 -04:00
co-authored by Claude Sonnet 5
parent 8251aebcf8
commit 2a2d7c5e5e
17 changed files with 90693 additions and 80 deletions
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experiments/bare_metal/latest/aarch64.csv
+21 -21
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@@ -71,25 +71,25 @@ tick_number,elapsed_ns,tick_interval_ns,cache_hits_delta,bucket_hits_delta,word_
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36,360000,10000,0,0,256,45,29,256,256,0,0,206,65536,0,1,65536,0,0
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88 29 290000 10000 0 0 256 45 24 512 512 0 0 161 163 65536 0 1 65536 0 0
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91 32 320000 10000 0 0 255 45 26 256 256 0 0 180 181 65536 0 1 65536 0 0
92 33 330000 10000 0 0 256 45 27 256 256 0 0 186 187 65536 0 1 65536 0 0
93 34 340000 10000 0 0 256 45 27 256 256 0 0 192 194 65536 0 1 65536 0 0
94 35 350000 10000 0 0 256 45 28 256 256 0 0 198 200 65536 0 1 65536 0 0
95 36 360000 10000 0 0 256 45 29 256 256 0 0 205 206 65536 0 1 65536 0 0