starkernel: converge the tick path and wire the adaptive heartbeat (item 0.8)
Introduces src/starkernel/heartbeat.c as the shared top/bottom-half implementation of heartbeat_init/tick/service/ticks/trust/state, replacing the per-architecture duplicates in amd64/riscv64/aarch64 timer.c. Each arch's timer.c now contributes only heartbeat_read_counter() (rdtsc / rdtime / CNTPCT_EL0). Per the GAP-A1 ruling the top half stays counter+ latch only; heartbeat_service() (called every REPL idle iteration, unconditionally per FABRIC.md's fidelity note) does the window/variance/ trust work outside interrupt context. vm_tick()'s call sites are unchanged -- the engine still runs on the virtual tick. Per FABRIC.md §26 (ruled 2026-08-03): wires Loop #7's execution-derived stable/volatile signal into the physical re-arm period. vm_runtime.c's existing Loop #7 site now calls heartbeat_set_adaptive_period_ns() with tick_target_ns ratio-rescaled onto a 10ms kernel base (not the hosted 10us HEARTBEAT_TICK_NS -- see §26.3 for the scale mismatch). Each architecture's re-arm function (apic_timer_rearm() on amd64/aarch64, riscv64_timer_rearm()) now converts heartbeat_next_period_ns() to its own raw counter units instead of a fixed constant; amd64 gained a rearm function it didn't previously need, since periodic-mode auto-reload never required one before this item. Verified: all three architectures build with no new warnings and boot cleanly to ok> with dict_hash=0x3d4e1daf289da94f, unchanged from the pre-change baseline -- no regression. Verified NOT achieved: live re-arm period variation under load. A temporary diagnostic (added and reverted) confirmed Loop #7 never actually fired during a live QEMU session -- a synthetic word-execution loop drove ~6,500 executions, past the 1000-tick inference frequency, without tripping vm_tick_inference_engine()'s pre-existing !vm->rolling_window.is_warm gate. That gate predates this item and was not investigated -- out of scope. FABRIC.md's Done-when is amended to record this honestly rather than claim it. Punch list §25 item 0.8 complete (per amended, weaker acceptance -- see the item's own annotation). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
co-authored by
Claude Sonnet 5
Claude Sonnet 5
parent
da4cb14702
commit
3699be964d
@@ -75,10 +75,6 @@ static uint64_t s_base_ns = 0; /* ns offset at timer_init() */
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static timer_calibration_record_t s_cal;
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/* ─── Heartbeat state ────────────────────────────────────────────────── */
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static TimeTrustState g_heartbeat;
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/* ─── timer_init ─────────────────────────────────────────────────────── */
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/*
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@@ -229,128 +225,19 @@ const timer_calibration_record_t *timer_calibration_record(void)
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/* ─── Heartbeat ──────────────────────────────────────────────────────── */
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/*
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* @brief Initialise the heartbeat rolling-window state.
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*
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* Zeroes the @c TimeTrustState @c g_heartbeat and sets up the expected
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* inter-tick interval as @c tsc_hz / @c tick_hz system-counter ticks. On
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* AArch64 "TSC" refers to @c CNTPCT_EL0; the variable name is preserved
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* for cross-ISA consistency.
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*
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* If either @p tsc_hz or @p tick_hz is zero, @c expected_delta falls back
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* to 10,000,000 ticks (≈ 160 ms at 62.5 MHz) which is a safe non-zero
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* sentinel preventing division-by-zero in the rolling window.
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*
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* Initial @c trust is set to @c Q48_ONE (full trust) because the ARM
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* Generic Timer is invariant by architecture and requires no initial
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* warm-up period unlike the x86 TSC.
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*
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* @param tsc_hz System counter frequency (Hz); from @c timer_tsc_hz().
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* @param tick_hz Heartbeat interrupt rate (Hz); from @c apic_timer_init().
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*/
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void heartbeat_init(uint64_t tsc_hz, uint64_t tick_hz)
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{
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g_heartbeat.ticks = 0;
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g_heartbeat.last_tsc = 0;
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g_heartbeat.total_samples = 0;
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g_heartbeat.variance = 0;
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g_heartbeat.trust = Q48_ONE;
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g_heartbeat.window.pos = 0;
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g_heartbeat.window.count = 0;
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for (int i = 0; i < TIME_WINDOW_SIZE; i++) {
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g_heartbeat.window.deltas[i] = 0;
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}
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g_heartbeat.expected_delta = (tick_hz > 0 && tsc_hz > 0)
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? (tsc_hz / tick_hz)
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: 10000000ULL;
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}
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/**
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* @brief Record one heartbeat tick and update the inter-tick deviation window.
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* @brief Read the raw counter the aarch64 heartbeat is paced against.
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*
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* Called from the timer ISR (or its AArch64 stub equivalent) at each
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* periodic heartbeat. Reads @c CNTPCT_EL0 and, if @c last_tsc is
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* non-zero, computes the signed deviation:
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* Item 0.8 (FABRIC.md §25.1): the shared heartbeat.c now owns
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* heartbeat_init()/heartbeat_tick()/heartbeat_service()/heartbeat_ticks()/
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* heartbeat_trust()/heartbeat_state() and the per-arch @c g_heartbeat
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* state that used to live in this file. This is the one piece that stays
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* per-architecture -- the same @c CNTPCT_EL0 the rest of this file's
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* calibration already reads via @c cntpct_read().
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*
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* @code
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* delta = (now - last_tsc) - expected_delta
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* @endcode
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*
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* Stores @p delta into the circular @c window.deltas[] buffer at position
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* @c (window.pos % TIME_WINDOW_SIZE) and advances the pointer. On AArch64,
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* @c trust is unconditionally set to @c Q48_ONE (full confidence) because
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* the Generic Timer is invariant and needs no statistical quality estimate.
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* The x86-64 path uses @c variance_to_trust() instead.
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*
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* Increments both @c total_samples (lifetime count) and @c ticks (monotonic
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* heartbeat counter used by @c heartbeat_ticks()).
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* @return Current @c CNTPCT_EL0 value.
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*/
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void heartbeat_tick(void)
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uint64_t heartbeat_read_counter(void)
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{
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uint64_t now = cntpct_read();
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if (g_heartbeat.last_tsc != 0) {
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int64_t delta = (int64_t)(now - g_heartbeat.last_tsc)
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- (int64_t)g_heartbeat.expected_delta;
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uint32_t pos = g_heartbeat.window.pos % TIME_WINDOW_SIZE;
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g_heartbeat.window.deltas[pos] = delta;
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g_heartbeat.window.pos++;
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if (g_heartbeat.window.count < TIME_WINDOW_SIZE) {
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g_heartbeat.window.count++;
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}
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g_heartbeat.total_samples++;
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}
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g_heartbeat.last_tsc = now;
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g_heartbeat.ticks++;
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g_heartbeat.trust = Q48_ONE; /* Simplified: full trust on ARM */
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}
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/**
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* @brief Return the total number of heartbeat ticks since @c heartbeat_init().
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*
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* @c ticks is incremented unconditionally on every @c heartbeat_tick() call,
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* including the first tick where no delta is recorded (because @c last_tsc
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* is still zero). It therefore counts timer interrupts from boot, not valid
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* delta samples.
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*
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* @return Monotonic tick counter; starts at 0, incremented at each heartbeat.
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*/
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uint64_t heartbeat_ticks(void)
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{
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return g_heartbeat.ticks;
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}
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/**
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* @brief Return the current TIME-TRUST quality metric in Q48.16 format.
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*
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* On AArch64 this always returns @c Q48_ONE (the value 1.0 in Q48.16,
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* i.e., @c 0x0000000000010000) because the ARM Generic Timer is invariant
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* by architecture and no statistical quality degradation is expected.
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*
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* The x86-64 implementation derives trust from the rolling-window variance
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* of inter-tick TSC deviations using @c variance_to_trust().
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*
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* @return TIME-TRUST as Q48.16; always @c Q48_ONE on AArch64.
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*/
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time_trust_t heartbeat_trust(void)
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{
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return g_heartbeat.trust;
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}
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/**
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* @brief Return a pointer to the heartbeat @c TimeTrustState.
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*
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* Provides read access to the full @c g_heartbeat structure for callers
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* that need to inspect the rolling window contents, variance estimate, or
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* expected delta — for example, the VM bootstrap parity collector
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* (@c sk_parity_collect()) and the @c sk_hal_time_trust() HAL accessor.
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*
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* The pointer is valid for the lifetime of the kernel (module-static storage).
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*
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* @return Pointer to @c g_heartbeat; never NULL.
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*/
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const TimeTrustState *heartbeat_state(void)
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{
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return &g_heartbeat;
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return cntpct_read();
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}
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