riscv64: PLIC bring-up, external-interrupt substrate (item 4.3.5b)

Punch list §25 item 4.3.5b complete.

sie.SEIE enabled, PLIC threshold/claim/complete wired into the trap
handler. Verified with a UART-loopback synthetic interrupt (PLIC has no
software set-pending register, unlike GICv2): claim_count=1, last_irq=10,
IIR confirms genuine receive-data cause, byte matched exactly. Self-test
code run once for evidence then fully reverted, per Captain Bob's ruling;
only the permanent substrate remains, no source enabled by default.
Three-arch acceptance boot clean, zero exceptions.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

Makefile.starkernel

@@ -423,6 +423,10 @@ LOADER_ARCH_SRCS += \
     $(KERNEL_SRC)/arch/$(ARCH)/ioapic.c \
     $(KERNEL_SRC)/arch/$(ARCH)/i8042.c
 endif
+ifeq ($(ARCH),riscv64)
+LOADER_ARCH_SRCS += \
+    $(KERNEL_SRC)/arch/$(ARCH)/plic.c
+endif
 else
 LOADER_SRCS_BASE := \
     $(KERNEL_SRC)/boot/uefi_loader.c \