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riscv64: PLIC bring-up, external-interrupt substrate (item 4.3.5b)

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Punch list §25 item 4.3.5b complete.

sie.SEIE enabled, PLIC threshold/claim/complete wired into the trap
handler. Verified with a UART-loopback synthetic interrupt (PLIC has no
software set-pending register, unlike GICv2): claim_count=1, last_irq=10,
IIR confirms genuine receive-data cause, byte matched exactly. Self-test
code run once for evidence then fully reverted, per Captain Bob's ruling;
only the permanent substrate remains, no source enabled by default.
Three-arch acceptance boot clean, zero exceptions.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
2026-08-08 11:24:47 -04:00
co-authored by Claude Sonnet 5
parent 36965cf812
commit 5f4df673c1
19 changed files with 73317 additions and 88 deletions
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capsules/BLOCK_MAP.md
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# Capsule Block Manifest — Auto-generated
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<!-- Generated by mkcapsule --manifest 2026-08-08T15:22:20Z -->
<!-- DO NOT EDIT — re-run mkcapsule --manifest to refresh. -->
<!-- Hand-written justifications and immutability notes live -->
<!-- in MANIFEST.md alongside this auto-generated index. -->