riscv64: PLIC bring-up, external-interrupt substrate (item 4.3.5b)
Punch list §25 item 4.3.5b complete. sie.SEIE enabled, PLIC threshold/claim/complete wired into the trap handler. Verified with a UART-loopback synthetic interrupt (PLIC has no software set-pending register, unlike GICv2): claim_count=1, last_irq=10, IIR confirms genuine receive-data cause, byte matched exactly. Self-test code run once for evidence then fully reverted, per Captain Bob's ruling; only the permanent substrate remains, no source enabled by default. Three-arch acceptance boot clean, zero exceptions. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
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co-authored by
Claude Sonnet 5
parent
36965cf812
commit
5f4df673c1
@@ -73,23 +73,23 @@ tick_number,elapsed_ns,tick_interval_ns,cache_hits_delta,bucket_hits_delta,word_
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19,190000,10000,0,0,256,39,16,4096,3224,0,0,112,65536,0,1,65536,0,0
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33,330000,10000,0,0,256,45,27,256,256,0,0,217,65536,0,1,65536,0,0
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35,350000,10000,0,0,256,45,28,256,256,0,0,232,65536,0,1,65536,0,0
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36,360000,10000,0,0,256,45,29,256,256,0,0,239,65536,0,1,65536,0,0
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