riscv64: PLIC bring-up, external-interrupt substrate (item 4.3.5b)
Punch list §25 item 4.3.5b complete. sie.SEIE enabled, PLIC threshold/claim/complete wired into the trap handler. Verified with a UART-loopback synthetic interrupt (PLIC has no software set-pending register, unlike GICv2): claim_count=1, last_irq=10, IIR confirms genuine receive-data cause, byte matched exactly. Self-test code run once for evidence then fully reverted, per Captain Bob's ruling; only the permanent substrate remains, no source enabled by default. Three-arch acceptance boot clean, zero exceptions. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
co-authored by
Claude Sonnet 5
Claude Sonnet 5
parent
36965cf812
commit
5f4df673c1
@@ -6,14 +6,17 @@
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/**
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* apic.c (riscv64) - APIC stub. No Local APIC on RISC-V; interrupt
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* controller is PLIC (Platform-Level Interrupt Controller). These stubs
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* satisfy the common kernel interface; PLIC wiring is a later milestone.
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* controller is PLIC (Platform-Level Interrupt Controller). apic_init()
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* calls into plic.c for the real PLIC bring-up (item 4.3.5b); apic_eoi()
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* stays a no-op since PLIC completion happens per-source in the trap
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* handler (claim/complete), not via a single shared EOI register.
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*/
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#include "apic.h"
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#include "uefi.h"
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#include "console.h"
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#include "timer.h"
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#include "starkernel/plic.h"
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#include <stdint.h>
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static uint64_t s_timer_period_tsc = 0;
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@@ -149,20 +152,23 @@ void riscv64_timer_rearm(void)
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}
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/*
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* @brief Initialise the interrupt controller (RISC-V PLIC stub).
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* @brief Initialise the interrupt controller: PLIC bring-up (item 4.3.5b).
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*
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* On x86-64 this function configures the Local APIC. On RISC-V the
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* Platform-Level Interrupt Controller (PLIC) handles external interrupt
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* routing; PLIC bring-up is deferred to a later milestone. This stub
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* satisfies the common @c apic_init() call site in @c kernel_main()
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* and always returns success.
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* routing -- @c plic_init() (arch/riscv64/plic.c) maps it, sets the S-mode
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* context's threshold, and enables @c sie.SEIE. No source is enabled here;
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* that is each future consumer's own job (4.3.5c for virtio-keyboard).
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*
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* @param boot_info Kernel boot information (ACPI/PLIC base address); unused.
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* @param boot_info Kernel boot information; unused (PLIC base is a verified
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* constant, not discovered from @c boot_info->dtb -- see
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* plic.c's file header for why).
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* @return 0 always.
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*/
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int apic_init(BootInfo *boot_info)
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{
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(void)boot_info;
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plic_init();
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return 0;
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}
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@@ -12,6 +12,7 @@
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#include "arch.h"
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#include "console.h"
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#include "starkernel/timer.h"
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#include "starkernel/plic.h"
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volatile const char *g_sk_fault_word = (void *)0;
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@@ -24,10 +25,18 @@ extern void riscv64_install_vectors(void);
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extern void riscv64_timer_rearm(void);
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/* scause cause codes for supervisor-mode interrupts (RISC-V Privileged Spec
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* §4.1.9, Table "Supervisor cause register values"). Only the timer is used;
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* software (1) and external (9) interrupts are not enabled. */
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* §4.1.9, Table "Supervisor cause register values"). */
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#define SCAUSE_INTERRUPT_BIT (1ULL << 63)
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#define SCAUSE_S_TIMER 5ULL
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#define SCAUSE_S_EXTERNAL 9ULL
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/* Count of real PLIC claims serviced since boot (item 4.3.5b). Cheap
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* standing diagnostic, same shape as amd64's g_i8042_isr_count/
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* g_spurious_count -- confirms the claim/dispatch/complete path is alive
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* without needing a live debugger. Nothing enables any PLIC source by
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* default, so this stays 0 unless a future consumer (or a live test)
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* explicitly calls plic_enable(). */
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volatile uint32_t g_plic_claim_count = 0;
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/**
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* @brief Dispatch an asynchronous supervisor interrupt.
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@@ -42,9 +51,17 @@ extern void riscv64_timer_rearm(void);
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* permanently and silently. Ordering it ahead of @c heartbeat_tick() means a
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* fault in the bookkeeping cannot also cost the next tick.
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*
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* Supervisor external (cause 9, item 4.3.5b): claim/dispatch/complete
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* through the PLIC. No source is enabled by default (see plic.c), so this
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* branch is normally never reached; a future consumer enabling its own
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* source is what makes it fire. Dispatch here is deliberately generic --
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* this item is pure PLIC substrate, not a device driver -- a future
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* consumer (4.3.5c) is expected to extend this with real per-source
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* handling, the same way i8042's keyboard branch sits in amd64's
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* isr_common_handler().
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*
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* Any other cause is ignored rather than fatal: an unexpected-but-harmless
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* asynchronous interrupt should not take the kernel down, and none are
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* currently enabled to arrive.
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* asynchronous interrupt should not take the kernel down.
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*
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* @param scause Raw @c scause value, interrupt bit still set.
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*/
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@@ -55,6 +72,12 @@ void riscv64_interrupt_handler(uint64_t scause)
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if (cause == SCAUSE_S_TIMER) {
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riscv64_timer_rearm();
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heartbeat_tick();
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} else if (cause == SCAUSE_S_EXTERNAL) {
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uint32_t irq = plic_claim();
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if (irq != 0) {
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g_plic_claim_count++;
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plic_complete(irq);
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}
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}
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}
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@@ -0,0 +1,90 @@
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/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James. All rights reserved.
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Licensed under the StarForth License, Version 1.0.
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*/
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/**
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* plic.c (riscv64) - Platform-Level Interrupt Controller driver
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*
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* Item 4.3.5b. Register layout (priority/pending/enable/threshold/claim-
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* complete) is the standard SiFive PLIC-1.0.0 layout QEMU implements --
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* architectural, not board-specific, same status as the GICD/GICC register
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* *offsets* item 0.6 cross-checked against the Linux arm-gic header.
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*
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* PLIC_BASE and PLIC_CONTEXT_S are QEMU-virt-specific and were NOT
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* hardcoded from memory: verified 2026-08-08 via
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* `qemu-system-riscv64 -machine virt,dumpdtb=...`, decoded with a script
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* using this tree's own fdt.c parsing logic (not dtc, which is not
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* installed). The real devicetree shows:
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* soc/plic@c000000: compatible = "sifive,plic-1.0.0","riscv,plic0",
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* reg = <0x0 0xc000000 0x0 0x600000>, riscv,ndev = 95
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* soc/plic@c000000: interrupts-extended = <&cpu0-intc 11 &cpu0-intc 9>
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* -- two contexts for hart 0: context 0 feeds cause 11 (MEIE, M-mode
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* external), context 1 feeds cause 9 (SEIE, S-mode external). Context
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* index is position in this list, confirmed rather than assumed.
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* soc/serial@10000000 (ns16550a): interrupts = <10>, interrupt-parent =
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* &plic -- PLIC source 10, matching console.c's existing NS16550_BASE.
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* Confirmed for this exact QEMU 10.2.1 build; not assumed stable across
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* versions, same caveat item 0.6 recorded for its own dumped values.
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*
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* No live in-kernel node-scoped devicetree lookup here even though
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* riscv64 DTB access does work (unlike aarch64): fdt.c's fdt_find_prop()
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* is a flat, whole-tree search by property *name*, which is exactly right
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* for a globally-unique name like "timebase-frequency" (already used by
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* timer.c) but wrong for "reg" -- that name recurs on nearly every node,
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* so a flat search would return the wrong node's base address. Finding
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* PLIC's own reg specifically needs node-scoped (by-compatible) lookup,
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* which does not exist in fdt.c and is a bigger addition than this item's
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* stated scope (PLIC programming, not a general devicetree query engine).
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*/
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#include <stdint.h>
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#include "starkernel/plic.h"
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#include "console.h"
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#define PLIC_BASE 0x0C000000UL
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#define PLIC_CONTEXT_S 1u /* S-mode, hart 0 -- verified, see file header */
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#define PLIC_PRIORITY(irq) (PLIC_BASE + 4u * (irq))
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#define PLIC_ENABLE(ctx) (PLIC_BASE + 0x2000u + 0x80u * (ctx))
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#define PLIC_THRESHOLD(ctx) (PLIC_BASE + 0x200000u + 0x1000u * (ctx))
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#define PLIC_CLAIM(ctx) (PLIC_BASE + 0x200004u + 0x1000u * (ctx))
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static inline volatile uint32_t *reg32(uintptr_t addr) {
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return (volatile uint32_t *)addr;
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}
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int plic_init(void) {
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/* Threshold 0 = maximally permissive. Safe: nothing is enabled at any
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* source yet, so nothing can actually reach claim() until a caller
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* explicitly enables it. */
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*reg32(PLIC_THRESHOLD(PLIC_CONTEXT_S)) = 0;
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__asm__ volatile ("csrs sie, %0" :: "r"(1UL << 9) : "memory"); /* SEIE */
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console_println("PLIC: init (base=0x0c000000, S-mode context 1, threshold=0)");
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return 0;
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}
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void plic_set_priority(uint32_t irq, uint32_t priority) {
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*reg32(PLIC_PRIORITY(irq)) = priority;
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}
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void plic_enable(uint32_t irq) {
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volatile uint32_t *reg = reg32(PLIC_ENABLE(PLIC_CONTEXT_S) + 4u * (irq / 32u));
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*reg |= (1u << (irq % 32u));
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}
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void plic_disable(uint32_t irq) {
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volatile uint32_t *reg = reg32(PLIC_ENABLE(PLIC_CONTEXT_S) + 4u * (irq / 32u));
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*reg &= ~(1u << (irq % 32u));
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}
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uint32_t plic_claim(void) {
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return *reg32(PLIC_CLAIM(PLIC_CONTEXT_S));
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}
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void plic_complete(uint32_t irq) {
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*reg32(PLIC_CLAIM(PLIC_CONTEXT_S)) = irq;
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}
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