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ACL-TTL overhead: paired 18-cell measurement complete, FABRIC-2.md Section P

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Full 18-cell paired campaign (9 arch/seed pairs x ACL disabled/enabled)
complete: 8,640/8,640 rows, all 16 cfg values x 30 each in every cell,
zero errors. Confirmed capsules/zuse.4th's ACL-ZUSE-BOOT self-pin bug
(self-pin placed inside its own colon definition, causing a genuine
forward-reference failure) is isolated from the core ACL enforcement
mechanism -- verified via live VM state query on multiple cells that
ACL-INIT-PRIMITIVES and EXEC/BYE pinning both complete correctly
regardless.

Result: +5.30% pooled overhead, +4.42% unweighted mean across the 9
pairs (sd 6.77%), paired t=2.043 (df=8) -- not significant at p<0.05.
Documented honestly as a real positive trend that doesn't establish a
precise percentage with confidence, given wall-clock timing's noise
floor is comparable to the effect size -- unlike the original ACL-RWT
campaign's VM-internal tick-counter methodology. A tighter measurement
(more replications, or reading a VM-internal counter directly) is
scoped as a next step, not attempted here.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
2026-08-20 19:41:55 -04:00
co-authored by Claude Sonnet 5
parent 6a71f503a4
commit 6e7323b3b8
9 changed files with 49801 additions and 2 deletions
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experiments/bare_metal/runs/acl-ttl-overhead-20260820/timing.csv
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@@ -14,3 +14,6 @@ order,arch,seed,acl,start_ts,end_ts,elapsed_s,rows,cfgs_ok,errors
13,amd64,13579,enabled,1787267123.028308417,1787267323.547801480,200.519,480,TRUE,0
14,riscv64,67890,enabled,1787267448.631728414,1787267611.865221636,163.233,480,TRUE,0
15,aarch64,67890,disabled,1787267773.852755653,1787268053.955665900,280.103,480,TRUE,0
16,amd64,12345,enabled,1787268199.244061241,1787268398.506357104,199.262,480,TRUE,0
17,aarch64,67890,enabled,1787268581.129615111,1787268869.561021888,288.431,480,TRUE,0
18,amd64,67890,disabled,1787268989.639012724,1787269176.457316387,186.818,480,TRUE,0
1 order arch seed acl start_ts end_ts elapsed_s rows cfgs_ok errors
14 13 amd64 13579 enabled 1787267123.028308417 1787267323.547801480 200.519 480 TRUE 0
15 14 riscv64 67890 enabled 1787267448.631728414 1787267611.865221636 163.233 480 TRUE 0
16 15 aarch64 67890 disabled 1787267773.852755653 1787268053.955665900 280.103 480 TRUE 0
17 16 amd64 12345 enabled 1787268199.244061241 1787268398.506357104 199.262 480 TRUE 0
18 17 aarch64 67890 enabled 1787268581.129615111 1787268869.561021888 288.431 480 TRUE 0
19 18 amd64 67890 disabled 1787268989.639012724 1787269176.457316387 186.818 480 TRUE 0