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Record trajectory beyond v2.5.0: Zynq FPGA next, after a "coloring in" hardening phase

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The next big milestone after the three-board bare-metal cut (v2.5.0) is
transferring the battle-tested amd64/aarch64/riscv64 story to a Zynq (AMD
Xilinx) FPGA SoC — configurable silicon with soft/hard CPU cores, PL fabric,
and a non-standard memory map, a genuinely larger step than any prior board
(expected on a new even-major line). Between v2.5.0 and the Zynq sits a
"coloring in" period: hardening that thickens the shape of what exists rather
than adding silicon (USB BOT/xHCI + block robustness, live-entropy and
Zuse-cert hardening on real ASICs, SMP/multi-core + IRQ routing from the HAL
notes, driver breadth) so the FPGA carries a production-honest shape forward.

Authoritative form in ROADMAP.md "Beyond v2.5.0"; FABRIC-3.md tracks the same
horizon in the post-release section and re-points G.6's Next at the
v2.2.0/v2.4.0/v2.5.0 cadence.
This commit is contained in:
Robert Allan James
2026-08-29 10:28:22 -04:00
parent 25276ae359
commit 8e94522d10
4 changed files with 36 additions and 4 deletions
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FABRIC-3.md
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@@ -3470,9 +3470,10 @@ this is what makes the image "as generic as possible."
(READ CAPACITY10 → MSC device ready → READ10 CSW PASS). This mirrors the real SER5 flow:
firmware boots the thumbdrive's ESP, and the OS's own storage rides the same USB BOT/xHCI
path. Works for all three arches via the arch-mapped EFI boot name.
- **Next (v2.0.1):** G.4 requires real entropy on the SER5 — amd64 **RDRAND** backend behind
`rng_get_bytes()` (QEMU-verifiable: `qemu64` exposes RDRAND), then flashing this image to
a physical stick and the G.5 real-board boot attempt.
- **Next (v2.0.1→v2.2.0):** G.5 real-board proof on the SER5 (in hand) — boot the thumbdrive
image, live RDRAND entropy, real Zuse mint on a second stick — then extend per arch to
v2.4.0 (RasPi 5) and v2.5.0 (Milk-V). Authoritative cadence in `ROADMAP.md`
"Board-by-board hardware rollout".
---
@@ -3492,3 +3493,13 @@ the punch lists above explicitly delimit what is excluded from each milestone:
- Dirty-event granularity (1.11, blocked on 4.3) and the §17.4 framebuffer heat/decay design.
- Re-run the DoE on the new substrate (§A 5.1).
- First-touch allocation first-call-free.
**Beyond v2.5.0 — Zynq FPGA, then a coloring-in period, decided 2026-08-29.** The next big
milestone after the three-board bare-metal cut (v2.5.0) is transferring the story to a
**Zynq FPGA** (configurable silicon — soft/hard cores, PL fabric, non-standard memory map) —
a genuinely larger step than any prior board, expected on a new even-major line. Between
v2.5.0 and starting the Zynq sits a **"coloring in"** hardening phase: making v2.5.0's
real-hardware story production-honest (USB BOT/xHCI + block robustness; live-entropy and
Zuse-cert hardening on real ASICs; SMP/multi-core + IRQ routing from the HAL notes; driver
breadth) so the FPGA carries a thickened, not thin, shape forward. Full form in
`ROADMAP.md` "Beyond v2.5.0 — Zynq FPGA is the next big milestone".