diff --git a/FABRIC-3.md b/FABRIC-3.md
index 5054765..9f05dc6 100644
--- a/FABRIC-3.md
+++ b/FABRIC-3.md
@@ -419,3 +419,36 @@ for at all today (amd64/aarch64/riscv64 only), not another board under an existi
 - **Boot modes**: eMMC, microSD, serial, USB.
 - Sources: [element14 — BBB product page](https://www.element14.com/community/docs/DOC-84108/l/beaglebone-black-development-board-with-1ghz-am335x-arm%C3%A3%C3%A2-cortex-a8-processor),
   [TI.com — BEAGL-BONE-BLACK](https://www.ti.com/tool/BEAGL-BONE-BLACK).
+
+### Noted for later, not yet in scope — Zynq-7000 (Puzhi PZ7010/PZ7020 "StarLite")
+
+Added per direct instruction 2026-09-04, **recorded only — no work scoped around it yet.**
+Unlike BeagleBone Black above, this one isn't a random addition: `ROADMAP.md` already names
+**Zynq FPGA as the next big milestone beyond v2.5.0** — "the step where the battle-tested
+amd64/aarch64/riscv64 story rides on configurable silicon," and the three-product split
+decided alongside it names "hardware steady-state machinery with sealed executions,
+HOL-proven" as the FPGA-native product this board would ultimately serve. This entry just
+puts a concrete, purchasable board under that already-named milestone.
+
+- **Board**: Puzhi PZ7010-StarLite (XC7Z010) or PZ7020-StarLite (XC7Z020) — same board design,
+  two SoC variants. 90×60mm, black PCB, immersion gold finish.
+- **SoC: Xilinx/AMD Zynq-7000**, combining a **Processing System (PS)** — dual-core ARM
+  Cortex-A9, up to 667 MHz (`-1` speed grade) or 800 MHz (`-2`, XC7Z020 only) — with
+  **Programmable Logic (PL)**, 28 nm Artix-7/Kintex-7-based FPGA fabric. Genuinely a fifth
+  architecture class in this reference: ARMv7-A again (like BeagleBone Black), but a
+  different core (Cortex-A9 vs. A8) *and* an FPGA fabric with no equivalent on any board
+  above — this is the "configurable silicon" milestone `ROADMAP.md` already flagged as
+  reshaping the hardware story (soft/hard CPU cores, PL fabric, non-standard memory map,
+  custom peripherals), not a small per-board addition even in concept.
+- **PS details** (identical between both variants): 256 KB on-chip memory, DDR3 controller,
+  32 KB I-cache + 32 KB D-cache per core, 512 KB shared L2.
+- **PL resources (the actual XC7Z010 vs. XC7Z020 difference)**: XC7Z010 — 4,400 logic slices,
+  17,600 6-input LUTs, 35,200 flip-flops, 270 KB block RAM, 80 DSP slices. XC7Z020 — 13,300
+  logic slices, 53,200 LUTs, 106,400 flip-flops, 630 KB block RAM, 220 DSP slices.
+- **RAM/storage**: 512 MB/1 GB DDR3, QSPI flash, EEPROM, SD boot.
+- **I/O**: JTAG, UART, HDMI out, Gigabit Ethernet, USB 2.0 host, 40-pin expansion; MIPI CSI on
+  the 7020 variant only.
+- Sources: [Puzhi — PZ7010-StarLite](https://www.en.puzhi.com/Product/AMD-FPGA-Development-Board/Zynq-7000-SoC/PZ7010-StarLite),
+  [Puzhi — PZ7020-StarLite](https://www.en.puzhi.com/Product/AMD-FPGA-Development-Board/Zynq-7000-SoC/PZ7020-StarLite),
+  [Xilinx/AMD — Zynq-7000 SoC Data Sheet (DS190)](https://www.mouser.com/datasheet/2/903/ds190-Zynq-7000-Overview-1595492.pdf),
+  [PCBSync — XC7Z010 vs XC7Z020 comparison](https://pcbsync.com/xilinx-xc7z010/).