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Record the FPGA three-product split: Hosted StarForth / full StarshipOS / HOL-proven sealed-execution hardware

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The Zynq FPGA is not a fourth platform to port to — it is the pivot that
forces the project into three distinct products, each with its own host,
delivery, and proof character (decided 2026-08-29):

  1. Hosted StarForth - the existing hosted/interpreted StarForth runtime
     (3-arch acceptance-tested), delivered as a portable embedded runtime.
  2. A full StarshipOS - the standalone OS built on LithosAnanke
     (LithosAnanke -> StarshipOS), a self-booting OS on general silicon
     (SER5/RasPi/Milk-V line).
  3. Hardware steady-state machinery with sealed executions, HOL-proven -
     the FPGA-native product: hardware-enforced sealed executions and
     steady-state machinery machine-checked in a proof assistant (HOL);
     delivery is the bitstream + HOL proof artifacts, not just an OS port.

The coupling is the point: product 3 is born on the FPGA, and its existence
is what cleanly separates 1 from 2 from 3. Product 1 ships hosted on an OS,
product 2 as an OS on general silicon, product 3 as proven hardware. Per-
product gates and the even-major line carrying the three as separate tracks
are scoped at v2.5.0 close / during the coloring-in phase. Complements, and
does not retract, the existing hardware bare-metal release policy.

Authoritative form in ROADMAP.md; FABRIC-3.md tracks the same horizon.
This commit is contained in:
Robert Allan James
2026-08-29 10:30:09 -04:00
parent 8e94522d10
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@@ -3501,5 +3501,14 @@ a genuinely larger step than any prior board, expected on a new even-major line.
v2.5.0 and starting the Zynq sits a **"coloring in"** hardening phase: making v2.5.0's
real-hardware story production-honest (USB BOT/xHCI + block robustness; live-entropy and
Zuse-cert hardening on real ASICs; SMP/multi-core + IRQ routing from the HAL notes; driver
breadth) so the FPGA carries a thickened, not thin, shape forward. Full form in
`ROADMAP.md` "Beyond v2.5.0 — Zynq FPGA is the next big milestone".
breadth) so the FPGA carries a thickened, not thin, shape forward.
**The FPGA creates a three-product split, decided 2026-08-29.** The Zynq is the pivot that
forces the project into three distinct products, each with its own host, delivery, and proof
character: (1) **Hosted StarForth** — the existing hosted/interpreted StarForth runtime;
(2) **A full StarshipOS** — the standalone OS on general silicon (LithosAnanke → StarshipOS);
(3) **Hardware steady-state machinery with sealed executions, HOL-proven** — the FPGA-native
product: hardware-enforced sealed executions and steady-state machinery machine-checked in a
proof assistant (HOL); delivery is the bitstream + HOL proof artifacts. Product 3 is born on
the FPGA and its existence is what cleanly separates 1 from 2 from 3. Full form in
`ROADMAP.md` "Release Versioning Policy → The FPGA creates a three-product split".