ACL-TTL tick campaign checkpoint: 7/18 cells

amd64/12345/enabled, aarch64/13579/enabled, amd64/67890/enabled added.
All 480/480 rows, 0 errors.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
2026-08-21 14:01:11 -04:00
co-authored by Claude Sonnet 5
parent d90f28b9da
commit c1622aaba8
6 changed files with 48342 additions and 1 deletions
+1 -1
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@@ -1,5 +1,5 @@
# Capsule Block Manifest — Auto-generated
<!-- Generated by mkcapsule --manifest 2026-08-21T17:39:29Z -->
<!-- Generated by mkcapsule --manifest 2026-08-21T17:56:38Z -->
<!-- DO NOT EDIT — re-run mkcapsule --manifest to refresh. -->
<!-- Hand-written justifications and immutability notes live -->
<!-- in MANIFEST.md alongside this auto-generated index. -->
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@@ -3,3 +3,6 @@ order,arch,seed,acl,before_tick,after_tick,delta_ticks,rows,errors
2,riscv64,12345,enabled,80,261304,261224,480,0
3,riscv64,12345,disabled,79,261142,261063,480,0
4,amd64,12345,disabled,79,261142,261063,480,0
5,amd64,12345,enabled,80,261304,261224,480,0
6,aarch64,13579,enabled,80,261299,261219,480,0
7,amd64,67890,enabled,80,261299,261219,480,0
1 order arch seed acl before_tick after_tick delta_ticks rows errors
3 2 riscv64 12345 enabled 80 261304 261224 480 0
4 3 riscv64 12345 disabled 79 261142 261063 480 0
5 4 amd64 12345 disabled 79 261142 261063 480 0
6 5 amd64 12345 enabled 80 261304 261224 480 0
7 6 aarch64 13579 enabled 80 261299 261219 480 0
8 7 amd64 67890 enabled 80 261299 261219 480 0
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