Artemis Milestone 2c: xHCI controller bring-up wired, DoE CSV export off by default

xhci_bringup() (HC reset, DCBAA, Command/Event rings, RUN/STOP) was
uncommitted and referenced an XHCI_WAIT_FOR macro that was never defined,
breaking the build. Wired all four wait sites to the existing
xhci_wait_bit() helper instead, matching each register/bit/polarity
needed (halt-before-reset waits for HCH set; HCRST, CNR, and post-RUN
HCH waits all wait for their bit to clear).

Also flipped g_doe_log_enabled's default from 1 to 0 -- the per-tick
[HADES][DOE] CSV export was flooding every boot log and slowing
interactive verification for no reason during ordinary acceptance runs;
HB-ON still re-enables it at the REPL for anyone running an actual DoE
campaign.

Three-arch acceptance: amd64/aarch64/riscv64 all boot clean to ok>,
zero DoE rows in any log. aarch64 and riscv64 both exited cleanly via
BYE with no exception, confirming the earlier SMC->HVC PSCI fix still
holds. Logs and DoE CSV artifacts from this run included.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01HZ8kNoTuP63pbQtro4qvrm

include/starkernel/xhci.h

@@ -55,6 +55,13 @@ typedef struct {
 #define XHCI_HCSPARAMS1_MAX_INTRS(v)  (((uint32_t)(v) >> 8)  & 0x7FFu)
 #define XHCI_HCSPARAMS1_MAX_PORTS(v)  (((uint32_t)(v) >> 24) & 0xFFu)
 
+/* HCSPARAMS2: Max Scratchpad Buffers is a 10-bit field split across two
+ * non-adjacent locations (xHCI 1.2 spec table 5-13) — Hi bits[25:21],
+ * Lo bits[31:27]. Zero means the controller needs no scratchpad buffers
+ * (common for simple emulated controllers, but verify live, not assumed). */
+#define XHCI_HCSPARAMS2_MAX_SCRATCHPAD_BUFS(v) \
+    ((((uint32_t)(v) >> 21) & 0x1Fu) << 5 | (((uint32_t)(v) >> 27) & 0x1Fu))
+
 /* -------------------------------------------------------------------------
  * Operational Registers (BAR0 + cap_length)
  * ------------------------------------------------------------------------- */