89 lines
3.8 KiB
TeX
89 lines
3.8 KiB
TeX
%% SCRAP: archive/GAP_ANALYSIS
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%% SOURCE: docs/working/archive/GAP_ANALYSIS.md
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%% STATUS: HISTORICAL
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%% FITS: none
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%% EDITORIAL: lifted — prose rewritten to press voice
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\section{Gap Analysis: Evolutionary Path to FPGA}
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Conducted on 2025-12-14, this gap analysis documents the thirty-seven
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critical components missing between the then-current StarForth VM and the
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four-stage evolutionary target: StarForth hosted VM $\to$ StarKernel
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(bare metal) $\to$ StarshipOS (self-hosting OS) $\to$ FPGA hardware
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processor. The record is preserved as a historical planning artefact;
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the majority of StarKernel gaps (Stages~1--2) have since been closed by
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LithosAnanke~v1.0.8.
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\subsection{State at Time of Analysis}
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StarForth was a working FORTH-79 VM with a physics-driven adaptive runtime,
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0\% algorithmic variance proven across ninety runs, and support for Linux
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and L4Re. Documentation was strong: formal ontology, nine scientific
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defence documents, HAL architecture documentation, and peer-review
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materials. Build tooling included forty-plus Makefile targets, PGO
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support, and a Design of Experiments framework.
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\subsection{Gaps by Evolutionary Stage}
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\subsubsection{Stage 1 — Hardware Abstraction Layer (Foundation)}
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Eight critical gaps were identified (H1--H8): HAL headers for time,
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interrupt, memory, console, CPU, and panic; a Linux HAL implementation;
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and migration of the VM core to the HAL. The analysis concluded that
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HAL implementation was the critical path: no progress toward StarKernel
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or FPGA was possible without it. Estimated effort: two to three weeks.
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\subsubsection{Stage 2 — StarKernel (Bare Metal Boot)}
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Eight critical gaps (K1--K8) and five important gaps (K9--K13) covered
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the UEFI boot loader, physical memory manager, virtual memory manager,
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kernel heap allocator, GDT/IDT setup, UART driver, TSC/HPET time
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sources, and APIC interrupt controller. Estimated source volume: eight
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to ten thousand lines of C and assembly; estimated elapsed time to a
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serial ``ok'' prompt: six to eight weeks.
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\subsubsection{Stage 3 — StarshipOS (Full OS)}
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Five critical gaps (OS1--OS5) addressed storage drivers, a filesystem,
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block device abstraction, TCP/IP stack, and network drivers. Seven
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important gaps (OS6--OS12) covered the process model, scheduler, IPC
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mechanism, device model, security/capabilities, system call interface,
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and userland tools. Estimated source volume: fifty thousand lines;
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estimated elapsed time: twelve to eighteen months.
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\subsubsection{Stage 4 — FPGA Implementation}
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Eight critical gaps (F1--F8) and eleven additional gaps (F9--F19) spanned
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feasibility study, HDL architecture, instruction set design, stack and
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dictionary memory, memory controller, I/O IP cores, HDL language and
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target FPGA selection, clock domain crossing, adaptive runtime in
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hardware, synthesis constraints, and toolchain setup. The FPGA path
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was described as entirely greenfield; estimated source volume: twenty to
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thirty thousand lines of Verilog or VHDL.
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\subsection{Critical Path}
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The dependency graph placed HAL implementation (H1--H8) as the sole
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gateway to all downstream work. Neither the StarKernel path nor the FPGA
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path could begin until platform independence was established.
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\subsection{Risk Assessment}
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The highest technical-uncertainty risks were FPGA feasibility (F1) and
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implementing the adaptive runtime in HDL (F12). The most resource-constrained
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risk was the aggregate project scope: approximately ninety-three thousand
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lines of new code representing twenty-eight to forty-two person-months of
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solo effort.
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\subsection{Total Gap Count}
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\begin{itemize}
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\item Critical: 12
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\item Important: 15
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\item Nice-to-have: 10
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\item \textbf{Total: 37}
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\end{itemize}
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The analysis recommended that the FPGA path receive a formal go/no-go
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feasibility decision (F1) before committing resources to HDL development.
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