Robert Allan JamesandClaude Sonnet 5
6e7323b3b8
Full 18-cell paired campaign (9 arch/seed pairs x ACL disabled/enabled) complete: 8,640/8,640 rows, all 16 cfg values x 30 each in every cell, zero errors. Confirmed capsules/zuse.4th's ACL-ZUSE-BOOT self-pin bug (self-pin placed inside its own colon definition, causing a genuine forward-reference failure) is isolated from the core ACL enforcement mechanism -- verified via live VM state query on multiple cells that ACL-INIT-PRIMITIVES and EXEC/BYE pinning both complete correctly regardless. Result: +5.30% pooled overhead, +4.42% unweighted mean across the 9 pairs (sd 6.77%), paired t=2.043 (df=8) -- not significant at p<0.05. Documented honestly as a real positive trend that doesn't establish a precise percentage with confidence, given wall-clock timing's noise floor is comparable to the effect size -- unlike the original ACL-RWT campaign's VM-internal tick-counter methodology. A tighter measurement (more replications, or reading a VM-internal counter directly) is scoped as a next step, not attempted here. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
1.6 KiB
1.6 KiB
| 1 | order | arch | seed | acl | start_ts | end_ts | elapsed_s | rows | cfgs_ok | errors |
|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 1 | riscv64 | 12345 | disabled | 1787246865.003797220 | 1787247037.443151234 | 172.439 | 480 | TRUE | 0 |
| 3 | 2 | riscv64 | 12345 | enabled | 1787247549.357850085 | 1787247707.475092723 | 158.117 | 480 | TRUE | 0 |
| 4 | 3 | aarch64 | 13579 | disabled | 1787248108.701960810 | 1787248383 | 274.298 | 480 | TRUE | 0 |
| 5 | 4 | aarch64 | 12345 | enabled | 1787263540.138566609 | 1787263850.633268709 | 310.495 | 480 | TRUE | 0 |
| 6 | 5 | riscv64 | 13579 | disabled | 1787263959.600081018 | 1787264116.655408410 | 157.055 | 480 | TRUE | 0 |
| 7 | 6 | aarch64 | 12345 | disabled | 1787264494.120355867 | 1787264777.160787083 | 283.040 | 480 | TRUE | 0 |
| 8 | 7 | aarch64 | 13579 | enabled | 1787264974.177469213 | 1787265291.239105652 | 317.062 | 480 | TRUE | 0 |
| 9 | 8 | amd64 | 13579 | disabled | 1787265488.338670740 | 1787265680.056553038 | 191.718 | 480 | TRUE | 0 |
| 10 | 9 | amd64 | 12345 | disabled | 1787265875.831736966 | 1787266064.967044192 | 189.135 | 480 | TRUE | 0 |
| 11 | 10 | amd64 | 67890 | enabled | 1787266216.072579477 | 1787266416.714834209 | 200.642 | 480 | TRUE | 0 |
| 12 | 11 | riscv64 | 13579 | enabled | 1787266537.716776416 | 1787266701.705197579 | 163.988 | 480 | TRUE | 0 |
| 13 | 12 | riscv64 | 67890 | disabled | 1787266808.730892518 | 1787266975.164517195 | 166.434 | 480 | TRUE | 0 |
| 14 | 13 | amd64 | 13579 | enabled | 1787267123.028308417 | 1787267323.547801480 | 200.519 | 480 | TRUE | 0 |
| 15 | 14 | riscv64 | 67890 | enabled | 1787267448.631728414 | 1787267611.865221636 | 163.233 | 480 | TRUE | 0 |
| 16 | 15 | aarch64 | 67890 | disabled | 1787267773.852755653 | 1787268053.955665900 | 280.103 | 480 | TRUE | 0 |
| 17 | 16 | amd64 | 12345 | enabled | 1787268199.244061241 | 1787268398.506357104 | 199.262 | 480 | TRUE | 0 |
| 18 | 17 | aarch64 | 67890 | enabled | 1787268581.129615111 | 1787268869.561021888 | 288.431 | 480 | TRUE | 0 |
| 19 | 18 | amd64 | 67890 | disabled | 1787268989.639012724 | 1787269176.457316387 | 186.818 | 480 | TRUE | 0 |