Robert Allan JamesandClaude Sonnet 5
f2e3bb1a90
Section T -- +0.0603%, final accepted figure Extended Section S's 3-seed/9-pair campaign to 6 seeds/18 pairs (36 cells) per Captain Bob's request for a fuller campaign before moving on. All 36 cells: 480/480 rows, 0 errors, 17,280/17,280 rows total. Every one of 18 disabled cells reads exactly 261063 ticks -- CV=0.000% across all 3 architectures and 6 seeds, zero exceptions. Every enabled cell's tick count is fully determined by seed alone, identical across all 3 architectures, zero exceptions. Pooled overhead across all 18 pairs: +0.0603% (mean +0.0603%, stdev 0.0008%, range +0.0598%- +0.0617%) -- statistically indistinguishable from Section S's 9-pair figure, now confirmed over double the data with 3 entirely new seeds. This closes the ACL-TTL overhead measurement line of investigation (Sections P, Q, R, S, T). +0.0603% is the final accepted figure. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
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1.7 KiB
| 1 | order | arch | seed | acl | before_tick | after_tick | delta_ticks | rows | errors |
|---|---|---|---|---|---|---|---|---|---|
| 2 | 1 | amd64 | 13579 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 3 | 2 | riscv64 | 12345 | enabled | 80 | 261304 | 261224 | 480 | 0 |
| 4 | 3 | riscv64 | 12345 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 5 | 4 | amd64 | 12345 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 6 | 5 | amd64 | 12345 | enabled | 80 | 261304 | 261224 | 480 | 0 |
| 7 | 6 | aarch64 | 13579 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 8 | 7 | amd64 | 67890 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 9 | 8 | aarch64 | 12345 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 10 | 9 | aarch64 | 67890 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 11 | 10 | riscv64 | 67890 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 12 | 11 | aarch64 | 67890 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 13 | 12 | amd64 | 67890 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 14 | 13 | riscv64 | 13579 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 15 | 14 | aarch64 | 12345 | enabled | 80 | 261304 | 261224 | 480 | 0 |
| 16 | 15 | riscv64 | 67890 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 17 | 16 | aarch64 | 13579 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 18 | 17 | riscv64 | 13579 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 19 | 18 | amd64 | 13579 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 20 | 19 | amd64 | 11111 | enabled | 80 | 261302 | 261222 | 480 | 0 |
| 21 | 20 | riscv64 | 24680 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 22 | 21 | riscv64 | 24680 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 23 | 22 | amd64 | 24680 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 24 | 23 | amd64 | 24680 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 25 | 24 | aarch64 | 11111 | enabled | 80 | 261302 | 261222 | 480 | 0 |
| 26 | 25 | amd64 | 99999 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 27 | 26 | aarch64 | 24680 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 28 | 27 | aarch64 | 99999 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 29 | 28 | riscv64 | 99999 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 30 | 29 | aarch64 | 99999 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 31 | 30 | amd64 | 99999 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 32 | 31 | riscv64 | 11111 | enabled | 80 | 261302 | 261222 | 480 | 0 |
| 33 | 32 | aarch64 | 24680 | enabled | 80 | 261299 | 261219 | 480 | 0 |
| 34 | 33 | riscv64 | 99999 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 35 | 34 | aarch64 | 11111 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 36 | 35 | riscv64 | 11111 | disabled | 79 | 261142 | 261063 | 480 | 0 |
| 37 | 36 | amd64 | 11111 | disabled | 79 | 261142 | 261063 | 480 | 0 |