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Checkpoint: paired ACL-TTL overhead measurement, 15/18 cells

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Cells 13-15 complete and verified (480/480 rows, 16/16 cfg coverage,
zero errors each): amd64/13579 enabled, riscv64/67890 enabled,
aarch64/67890 disabled. 3 cells remaining.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
2026-08-20 19:21:35 -04:00
co-authored by Claude Sonnet 5
parent becae2a763
commit 6a71f503a4
8 changed files with 49779 additions and 0 deletions
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experiments/bare_metal/runs/acl-ttl-overhead-20260820/timing.csv
+3
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@@ -11,3 +11,6 @@ order,arch,seed,acl,start_ts,end_ts,elapsed_s,rows,cfgs_ok,errors
10,amd64,67890,enabled,1787266216.072579477,1787266416.714834209,200.642,480,TRUE,0
11,riscv64,13579,enabled,1787266537.716776416,1787266701.705197579,163.988,480,TRUE,0
12,riscv64,67890,disabled,1787266808.730892518,1787266975.164517195,166.434,480,TRUE,0
13,amd64,13579,enabled,1787267123.028308417,1787267323.547801480,200.519,480,TRUE,0
14,riscv64,67890,enabled,1787267448.631728414,1787267611.865221636,163.233,480,TRUE,0
15,aarch64,67890,disabled,1787267773.852755653,1787268053.955665900,280.103,480,TRUE,0
1 order arch seed acl start_ts end_ts elapsed_s rows cfgs_ok errors
11 10 amd64 67890 enabled 1787266216.072579477 1787266416.714834209 200.642 480 TRUE 0
12 11 riscv64 13579 enabled 1787266537.716776416 1787266701.705197579 163.988 480 TRUE 0
13 12 riscv64 67890 disabled 1787266808.730892518 1787266975.164517195 166.434 480 TRUE 0
14 13 amd64 13579 enabled 1787267123.028308417 1787267323.547801480 200.519 480 TRUE 0
15 14 riscv64 67890 enabled 1787267448.631728414 1787267611.865221636 163.233 480 TRUE 0
16 15 aarch64 67890 disabled 1787267773.852755653 1787268053.955665900 280.103 480 TRUE 0