aarch64: detect exception level at runtime, cached accessor
Punch list §25 item 0.4 complete. Adds aarch64_current_el() in arch.c: reads CurrentEL[3:2] on first call, caches the result (CurrentEL cannot change post-ExitBootServices, so every consumer gets the same answer without repeating the MRS). Called from arch_interrupts_init() in interrupts.c -- the earliest point with both a working console (up since M1) and a genuine first consumer (vector installation is the first EL-dependent operation) -- and the detected level is printed to the boot log there. Declared via extern-in-place in interrupts.c rather than added to the shared arch.h: "exception level" has no amd64/riscv64 equivalent, matching the convention already used for riscv64_timer_rearm() in item 0.3. Verified on real QEMU output: "AArch64: running at EL1", correctly positioned immediately before "IDT installed." in the serial log. Boots clean, dict_hash 0x3d4e1daf289da94f unchanged from the item 0.1-0.3 baseline. Scope: this item establishes the detection and exposes it; it does not yet change VBAR/ELR/SPSR or timer-register selection to use it. arch_interrupts_init() still writes VBAR_EL1 unconditionally, and now says so explicitly in its own doc comment -- if aarch64_current_el() ever reports 2 on real hardware, exceptions taken at EL2 vector through VBAR_EL2, which nothing programs yet. That gap is items 0.5 (vectors/saved-state) and 0.7 (CNTP vs CNTHP) to close, per FABRIC.md's GAP-B3 finding. The boot-log EL2 case prints a note pointing at both. Only aarch64-scoped files touched (arch.c, interrupts.c) -- no shared loader or header changed, so amd64 and riscv64 are provably unaffected; not rebuilt for this item. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
co-authored by
Claude Sonnet 5
Claude Sonnet 5
parent
5784d8a1a8
commit
f43f3f4482
@@ -2049,7 +2049,7 @@ on until there is a tick on all three architectures (§16.1, §16.5).*
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configured rate within measurement noise. Verify the SBI extension is present before
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relying on it; if it is absent, stop and report rather than falling back silently.
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- [ ] **0.4 — aarch64: determine the exception level at runtime.**
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- [x] **0.4 — aarch64: determine the exception level at runtime.**
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Read `CurrentEL` once, early, and let it govern **everything EL-dependent**, not just the
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timer (B3): the vector base register (`VBAR_EL1` vs `VBAR_EL2` — today's `isr.S` writes
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`VBAR_EL1` unconditionally, which is never consulted for exceptions taken at EL2), the
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@@ -1,5 +1,5 @@
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# Capsule Block Manifest — Auto-generated
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<!-- Generated by mkcapsule --manifest 2026-08-03T22:22:04Z -->
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<!-- Generated by mkcapsule --manifest 2026-08-03T22:28:54Z -->
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<!-- DO NOT EDIT — re-run mkcapsule --manifest to refresh. -->
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<!-- Hand-written justifications and immutability notes live -->
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<!-- in MANIFEST.md alongside this auto-generated index. -->
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@@ -0,0 +1,59 @@
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tick_number,elapsed_ns,tick_interval_ns,cache_hits_delta,bucket_hits_delta,word_executions_delta,hot_word_count,avg_word_heat_q48,window_width,actual_window_size,predicted_label_hits,jitter_bits,apic_ticks,time_trust_q48,variance_q48,vm_call_depth_max,hera_heat_q48,hermes_heat_q48,artemis_heat_q48
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File diff suppressed because it is too large
Load Diff
@@ -14,6 +14,44 @@
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/* Installed by isr.S — installs VBAR_EL1 */
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extern void aarch64_install_vectors(void);
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/* -1 = not yet read. Cached rather than re-read on every call: CurrentEL
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* cannot change during the kernel's lifetime post-ExitBootServices, and a
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* cached value gives every consumer (vector install, GIC timer register
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* selection) the same answer without repeating the MRS. */
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static int s_current_el = -1;
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/**
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* @brief Return the AArch64 exception level the kernel is running at.
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*
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* Reads @c CurrentEL (bits [3:2] hold the EL number, [1:0] are RES0) on
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* first call and caches the result; every later call returns the cached
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* value. Safe to call at any point in boot, including before
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* @c console_init() — the read itself has no dependency, only the
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* printing of it does (see @c arch_interrupts_init() in @c interrupts.c,
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* the earliest point at which both this and a working console are
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* available).
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*
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* EDK2 on QEMU's aarch64 @c virt machine has been observed to leave the
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* kernel at either EL1 or EL2 depending on firmware build; nothing in this
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* tree may assume one over the other (FABRIC.md §25.7.1 GAP-B3). Every
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* EL-dependent choice — @c VBAR_EL1 vs @c VBAR_EL2, the @c ELR_ELx /
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* @c SPSR_ELx saved-state pair, and @c CNTP_*_EL0 vs @c CNTHP_*_EL2 — must
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* read this accessor rather than hardcode a level.
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*
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* @return 1 or 2. Never 0 or 3: a UEFI application that survived far enough
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* to reach this call cannot be running at EL0 (unprivileged) or EL3
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* (secure monitor — QEMU's virt firmware runs the kernel at EL1/EL2).
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*/
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int aarch64_current_el(void)
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{
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if (s_current_el < 0) {
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uint64_t current_el;
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__asm__ volatile ("mrs %0, CurrentEL" : "=r"(current_el));
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s_current_el = (int)((current_el >> 2) & 0x3);
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}
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return s_current_el;
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}
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/**
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* @brief Perform the earliest AArch64 architecture initialisation (no-op).
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*
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@@ -17,6 +17,12 @@ volatile const char *g_sk_fault_word = (void *)0;
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/* Defined in isr.S */
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extern void aarch64_install_vectors(void);
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/* Defined in arch.c. Extern-declared here rather than in the shared arch.h:
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* "exception level" has no amd64/riscv64 equivalent, so it does not belong
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* in the cross-ISA header — same convention as riscv64_timer_rearm() in
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* arch/riscv64/interrupts.c. */
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extern int aarch64_current_el(void);
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/**
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* @brief Print a 64-bit value as "0xNNNNNNNNNNNNNNNN" to the kernel console.
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*
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@@ -91,12 +97,26 @@ void aarch64_exception_handler(void)
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/**
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* @brief Install the AArch64 exception vector table (M4 milestone).
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*
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* Calls @c aarch64_install_vectors() (defined in @c isr.S) which writes
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* the address of the vector table base into @c VBAR_EL1 (Vector Base
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* Address Register, EL1). After this instruction all EL1 exceptions
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* First reads and reports the exception level via @c aarch64_current_el()
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* (punch-list item 0.4) — this is the earliest point in boot with both a
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* working console (up since M1) and a genuine need for the answer (vector
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* installation is the first EL-dependent operation). The read itself is
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* cheap and safe far earlier than this; only the console print is gated on
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* this call site.
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*
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* Then calls @c aarch64_install_vectors() (defined in @c isr.S) which
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* writes the address of the vector table base into @c VBAR_EL1 (Vector
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* Base Address Register, EL1). After this instruction all EL1 exceptions
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* (synchronous, IRQ, FIQ, SError) dispatch through the 512-byte-aligned
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* vector table assembled in @c isr.S.
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*
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* **@c VBAR_EL1 is written unconditionally regardless of the detected
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* level.** If @c aarch64_current_el() reports EL2, this is a known gap:
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* exceptions taken at EL2 vector through @c VBAR_EL2, which nothing here
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* programs, and installing EL2-aware vectors is punch-list item 0.5's
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* scope, not this one's. Item 0.4 establishes the detection every later
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* EL-dependent item must consult; it does not yet make use of it here.
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*
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* On AArch64 there is no IDT and no PIC to disable; the GIC replaces
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* both. The @c arch_interrupts_init() name is kept identical across all
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* ISAs so that @c kernel_main() can call the same symbol regardless of
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@@ -107,5 +127,12 @@ void aarch64_exception_handler(void)
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*/
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void arch_interrupts_init(void)
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{
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int el = aarch64_current_el();
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console_puts("AArch64: running at EL");
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console_putc((char)('0' + el));
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console_println(el == 2
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? " (VBAR_EL2/CNTHP_*_EL2 required — not yet wired, see item 0.5/0.7)"
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: "");
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aarch64_install_vectors();
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}
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