Robert Allan JamesandClaude Sonnet 5
9b6de5d6c7
plic_init() now takes boot_info->dtb (threaded through apic_init()) and tries fdt_find_node_by_compatible(dtb, "sifive,plic-1.0.0") -> fdt_find_prop_in_node(..., "reg", ...) before falling back to the QEMU-virt-specific constant it previously hardcoded unconditionally. Reuses the node-scoped DTB lookup primitive built for the aarch64 GIC base fix unchanged. s_plic_base is now a runtime uintptr_t, same shape as apic.c's s_gicd_base/s_gicc_base. This system's QEMU/UEFI riscv64 firmware does not forward a DTB to the guest (timer.c's own timebase-frequency read falls back too, confirmed in this boot's own log), so only the no-DTB fallback branch is exercised here -- the success branch (a real DTB with a matching PLIC node) stays unverified until real Milk-V Mars hardware. FABRIC-3.md's first-drafted claim that the success branch would run (based on a stale comment in plic.c's own pre-fix header) was checked against the actual log and corrected before this commit. 3-arch acceptance: amd64/aarch64 don't compile these files, so their runs are non-regression on untouched files only. riscv64's own boot log confirms the fallback path prints exactly as designed and boot reaches zuse)ok> unchanged. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_019YcT3H2PQeyujrzjqS3Var
64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James. All rights reserved.
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Licensed under the StarForth License, Version 1.0.
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*/
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/**
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* plic.h - Platform-Level Interrupt Controller interface (riscv64 only)
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*
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* Item 4.3.5a (FABRIC-0.md §27.5): Phase 0 (0.2/0.3) only ever enabled the
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* S-mode *timer* interrupt (sie.STIE). External interrupts (sie.SEIE) were
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* never touched, and the PLIC -- the only external-interrupt path on
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* RISC-V, there is no legacy PIC or I/O APIC equivalent -- had no driver
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* at all before this item. Pure substrate: this item wires the mechanism
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* (claim/dispatch/complete) with no permanent source enabled by default;
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* a real consumer (4.3.5b, virtio-keyboard) enables its own source later.
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*
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* @c plic_init() takes the boot DTB as of FABRIC-3.md §V.3 item 3's fix,
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* 2026-09-05: the base address was previously a QEMU-virt-specific
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* hardcoded constant, unconditionally wrong on the Milk-V Mars's real
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* JH7110 PLIC. See @c plic.c's file header for the discovery mechanism.
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*/
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#ifndef STARKERNEL_PLIC_H
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#define STARKERNEL_PLIC_H
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#include <stdint.h>
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/**
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* Map the PLIC and set the S-mode hart-0 context's priority threshold to 0
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* (maximally permissive -- safe because nothing is enabled at any source
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* by default; enabling a source is what actually lets it reach claim()).
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* Also sets sie.SEIE. Does not touch sstatus.SIE -- arch_enable_interrupts()
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* still owns that, same as the timer.
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*
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* @param dtb Candidate devicetree blob (@c BootInfo->dtb); NULL-safe. When
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* a real @c "sifive,plic-1.0.0" node is found, the PLIC base
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* address is read from its @c reg property; otherwise falls
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* back to the QEMU-virt-machine constant, unchanged from this
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* function's previous unconditional behaviour.
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* @return 0 on success.
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*/
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int plic_init(const void *dtb);
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/** Set a source's interrupt priority (1-7; 0 means "never interrupt"). */
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void plic_set_priority(uint32_t irq, uint32_t priority);
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/** Enable a source for the S-mode hart-0 context. */
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void plic_enable(uint32_t irq);
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/** Disable a source for the S-mode hart-0 context. */
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void plic_disable(uint32_t irq);
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/**
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* Claim the highest-priority pending interrupt for the S-mode hart-0
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* context. Returns the source ID, or 0 if none is pending.
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*/
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uint32_t plic_claim(void);
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/** Signal completion of the source previously returned by plic_claim(). */
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void plic_complete(uint32_t irq);
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#endif /* STARKERNEL_PLIC_H */
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