Robert Allan JamesandClaude Sonnet 5
a5cd1b76c8
amd64/24680/disabled, amd64/24680/enabled, aarch64/11111/enabled added. All 480/480 rows, 0 errors. Cross-arch consistency continues holding: seed 24680 gives 261219 on both riscv64 and amd64; seed 11111 gives 261222 on both amd64 and aarch64. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
26 lines
1.2 KiB
CSV
26 lines
1.2 KiB
CSV
order,arch,seed,acl,before_tick,after_tick,delta_ticks,rows,errors
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1,amd64,13579,enabled,80,261299,261219,480,0
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2,riscv64,12345,enabled,80,261304,261224,480,0
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3,riscv64,12345,disabled,79,261142,261063,480,0
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4,amd64,12345,disabled,79,261142,261063,480,0
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5,amd64,12345,enabled,80,261304,261224,480,0
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6,aarch64,13579,enabled,80,261299,261219,480,0
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7,amd64,67890,enabled,80,261299,261219,480,0
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8,aarch64,12345,disabled,79,261142,261063,480,0
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9,aarch64,67890,disabled,79,261142,261063,480,0
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10,riscv64,67890,enabled,80,261299,261219,480,0
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11,aarch64,67890,enabled,80,261299,261219,480,0
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12,amd64,67890,disabled,79,261142,261063,480,0
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13,riscv64,13579,enabled,80,261299,261219,480,0
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14,aarch64,12345,enabled,80,261304,261224,480,0
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15,riscv64,67890,disabled,79,261142,261063,480,0
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16,aarch64,13579,disabled,79,261142,261063,480,0
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17,riscv64,13579,disabled,79,261142,261063,480,0
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18,amd64,13579,disabled,79,261142,261063,480,0
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19,amd64,11111,enabled,80,261302,261222,480,0
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20,riscv64,24680,enabled,80,261299,261219,480,0
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21,riscv64,24680,disabled,79,261142,261063,480,0
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22,amd64,24680,disabled,79,261142,261063,480,0
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23,amd64,24680,enabled,80,261299,261219,480,0
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24,aarch64,11111,enabled,80,261302,261222,480,0
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