Robert Allan JamesandClaude Sonnet 5
f2e3bb1a90
Section T -- +0.0603%, final accepted figure Extended Section S's 3-seed/9-pair campaign to 6 seeds/18 pairs (36 cells) per Captain Bob's request for a fuller campaign before moving on. All 36 cells: 480/480 rows, 0 errors, 17,280/17,280 rows total. Every one of 18 disabled cells reads exactly 261063 ticks -- CV=0.000% across all 3 architectures and 6 seeds, zero exceptions. Every enabled cell's tick count is fully determined by seed alone, identical across all 3 architectures, zero exceptions. Pooled overhead across all 18 pairs: +0.0603% (mean +0.0603%, stdev 0.0008%, range +0.0598%- +0.0617%) -- statistically indistinguishable from Section S's 9-pair figure, now confirmed over double the data with 3 entirely new seeds. This closes the ACL-TTL overhead measurement line of investigation (Sections P, Q, R, S, T). +0.0603% is the final accepted figure. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
38 lines
1.7 KiB
CSV
38 lines
1.7 KiB
CSV
order,arch,seed,acl,before_tick,after_tick,delta_ticks,rows,errors
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1,amd64,13579,enabled,80,261299,261219,480,0
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2,riscv64,12345,enabled,80,261304,261224,480,0
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3,riscv64,12345,disabled,79,261142,261063,480,0
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4,amd64,12345,disabled,79,261142,261063,480,0
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5,amd64,12345,enabled,80,261304,261224,480,0
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6,aarch64,13579,enabled,80,261299,261219,480,0
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7,amd64,67890,enabled,80,261299,261219,480,0
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8,aarch64,12345,disabled,79,261142,261063,480,0
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9,aarch64,67890,disabled,79,261142,261063,480,0
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10,riscv64,67890,enabled,80,261299,261219,480,0
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11,aarch64,67890,enabled,80,261299,261219,480,0
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12,amd64,67890,disabled,79,261142,261063,480,0
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13,riscv64,13579,enabled,80,261299,261219,480,0
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14,aarch64,12345,enabled,80,261304,261224,480,0
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15,riscv64,67890,disabled,79,261142,261063,480,0
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16,aarch64,13579,disabled,79,261142,261063,480,0
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17,riscv64,13579,disabled,79,261142,261063,480,0
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18,amd64,13579,disabled,79,261142,261063,480,0
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19,amd64,11111,enabled,80,261302,261222,480,0
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20,riscv64,24680,enabled,80,261299,261219,480,0
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21,riscv64,24680,disabled,79,261142,261063,480,0
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22,amd64,24680,disabled,79,261142,261063,480,0
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23,amd64,24680,enabled,80,261299,261219,480,0
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24,aarch64,11111,enabled,80,261302,261222,480,0
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25,amd64,99999,enabled,80,261299,261219,480,0
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26,aarch64,24680,disabled,79,261142,261063,480,0
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27,aarch64,99999,disabled,79,261142,261063,480,0
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28,riscv64,99999,enabled,80,261299,261219,480,0
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29,aarch64,99999,enabled,80,261299,261219,480,0
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30,amd64,99999,disabled,79,261142,261063,480,0
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31,riscv64,11111,enabled,80,261302,261222,480,0
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32,aarch64,24680,enabled,80,261299,261219,480,0
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33,riscv64,99999,disabled,79,261142,261063,480,0
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34,aarch64,11111,disabled,79,261142,261063,480,0
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35,riscv64,11111,disabled,79,261142,261063,480,0
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36,amd64,11111,disabled,79,261142,261063,480,0
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