Files
LithosAnanake/experiments/bare_metal/runs/acl-ttl-overhead-20260821-ticks/ticks.csv
T
Robert Allan JamesandClaude Sonnet 5 e9d5353b6e ACL-TTL overhead: full 18-cell campaign complete, FABRIC-2.md Section S
-- +0.0604% mean, architecture-independent, fully deterministic

All 18 cells (9 arch/seed pairs x disabled/enabled, zuse-authenticated
throughout) complete: 8,640/8,640 rows, 0 errors. Every disabled cell
reads exactly 261063 ticks -- CV=0.000% across all 3 architectures and
3 seeds. Every enabled cell's tick count depends only on seed, identical
across all 3 architectures for a given seed. Pooled overhead: +0.0604%
(mean +0.0604%, stdev 0.0010%, range +0.0598%-+0.0617%).

This is now the accepted ACL-TTL overhead figure for this workload,
superseding Section P's invalidated wall-clock numbers (ACL never
actually armed) and refining Section R's single-pair pilot (+0.0448%,
n=1) to a tight, fully-reproducible, architecture-independent result
across 9 independent pairs.

One tooling bug fixed mid-campaign (cells 1-3): tick-extraction regex
missed the "[Hera] " console-tagger line prefix; underlying VM runs
were unaffected, affected cells' values recovered by hand from their
serial logs before the fix.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
2026-08-21 15:06:36 -04:00

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CSV

order,arch,seed,acl,before_tick,after_tick,delta_ticks,rows,errors
1,amd64,13579,enabled,80,261299,261219,480,0
2,riscv64,12345,enabled,80,261304,261224,480,0
3,riscv64,12345,disabled,79,261142,261063,480,0
4,amd64,12345,disabled,79,261142,261063,480,0
5,amd64,12345,enabled,80,261304,261224,480,0
6,aarch64,13579,enabled,80,261299,261219,480,0
7,amd64,67890,enabled,80,261299,261219,480,0
8,aarch64,12345,disabled,79,261142,261063,480,0
9,aarch64,67890,disabled,79,261142,261063,480,0
10,riscv64,67890,enabled,80,261299,261219,480,0
11,aarch64,67890,enabled,80,261299,261219,480,0
12,amd64,67890,disabled,79,261142,261063,480,0
13,riscv64,13579,enabled,80,261299,261219,480,0
14,aarch64,12345,enabled,80,261304,261224,480,0
15,riscv64,67890,disabled,79,261142,261063,480,0
16,aarch64,13579,disabled,79,261142,261063,480,0
17,riscv64,13579,disabled,79,261142,261063,480,0
18,amd64,13579,disabled,79,261142,261063,480,0